Many of today""s systems require flexible communication between a number of cooperating electronic nodes or modules, each having a microprocessor and one or more microcircuits. To avoid the need for a large number of individual conductors between each pair of nodes, serial transmission on a single data path is preferred. It is possible to connect each node with every other node, but once there are more than a few nodes, the connections become complex and expensive. For this reason, such connectivity structure is not particularly desirable. A number of communication protocols have been developed to deal with situations having many nodes and high message and data rates. Ethernet and the Internet are just two of the better-known serial transmission protocols having high data and message capacities. Unfortunately, these high capacities come at relatively high cost and complexity as well. These systems have relatively expensive individual nodes with high processing speeds justifying fast (and expensive) internode communication.
For communication systems having a relatively large number of nodes and relatively low message and data rates, it is economical and efficient to use a protocol providing each node with an inexpensive interface circuit. All of the interface circuits are connected to a single conductor pair, so each node can both transmit and receive on this conductor pair. The steadily falling cost of microprocessors and microcircuits generally, allows inexpensively creating such networks having scores or even hundreds of such nodes. One particular form of such a network uses the so-called CAN (controller area network) protocol. The CAN protocol establishes a mechanism for dealing with so-called collisions, which is the situation where a number of nodes transmit simultaneously.
In the CAN protocol, all of the nodes are connected to a single conductor pair. Data is transmitted from one node to all of the others in messages carried serially on the conductor pair. The messages are binarily encoded in the voltages on the conductor pair. Each message has a leading ID code that uniquely identifies the message, followed by a number of other fields of assigned length. The information in these fields includes the message length and the data itself. The CAN protocol uses hardware that treats one of the voltage levels assigned to one of the binary bit values as what is called dominant, the other recessive. Should two or more nodes transmit simultaneously causing colliding messages, a dominant voltage level transmitted by any node causes the conductor pair to carry a dominant voltage level during that time regardless of the number of other nodes simultaneously transmitting a recessive level. Each node monitors the signals carried on the conductor pair at all times. The nodes are programmed to transmit messages with prearranged ID codes.
Each node is programmed to continuously sense the message traffic on the conductor pair. When a node is not transmitting and detects in a message, an ID code to which it is programmed to respond, the node receives the message following and responds appropriately. While a node is transmitting, it continues to sense the signal on the conductor pair. When a node, during a bit time, is transmitting a recessive voltage and senses the voltage signal carried on the conductor pair is dominant, that means that a message collision is occurring, and the node transmitting the recessive voltage signal ceases transmitting. If two or more nodes are transmitting dominant voltage levels simultaneously, it may take several bit times before all of the collisions have been resolved. By assigning unique (to that node) leading ID codes for all of the messages sent by all of the nodes, eventually every node but one will detect a difference between its transmitted signal voltage and the conductor pair signal, leaving just that one node to transmit the remaining portion of its message. U.S. Pat. Nos. 5,001,642 and 5,303,348 describe the CAN protocol in more detail.
One advantage of the CAN protocol is the possibility for providing power conductors that many nodes can share. For example, the CAN protocol as originally conceived allows a pair of DC power conductor to be routed to each node along with the data conductors. It may even be possible in certain systems for data and power to share one or more common conductors. Thus, a four or even three wire bundle connecting all of the nodes can provide both power and communication for them.
As mentioned, some of these systems may have a large number of nodes. Miswiring during system assembly, or operational defects of an individual node after installation, creates a significant failure diagnosis problem. When reduced capability node hardware is involved, there is less opportunity for node-assisted diagnosis of node and system operating status. There may not be any sort of device in the node allowing human input signaling status of the nodes or changing node operation to assist trouble-shooting. Test instruments can detect failures in individual nodes of course, but this may require that the node be detached from the system, and of course requires either having a tester handy or calling a technician.
On a different point, certain distributed control systems, for example these used to control HVAC systems, have very low data rate requirements. Traditionally, these systems are designed to operate, in the U.S. anyway, with 60 Hz., 24 v. AC power. Conventionally, control elements such as thermostats, burner controls, and humidistats control the switching of power to the remotely sited air conditioners, furnaces, humidifiers, and blowers of the HVAC system.
We have developed a unique system employing certain principles of CAN architecture. This unique system provides advantages over the conventional system structure and yet easily integrates with a conventional and existing system. A number of novel features in this unique system assist in achieving this easy integration and enhance operation relative to these existing systems.
One of these features allows each of the nodes in the system to receive operating power from low voltage AC power, and at the same time use the 50 or 60 Hz. AC waveform for synchronizing the start of each bit interval for each node. In one embodiment, the two zero crossings of the power waveform per cycle synchronize the starts of 100 or 120 bit intervals each second. Such a system has a plurality of nodes for communicating with each other through messages encoded in a data signal comprising a series of data bits sent and received on a data line respectively to and from a data terminal of each node connected to the data line. The data bits are encoded in dominant and recessive signal levels corresponding to binary values and by which each said node resolves collisions of messages sent by more than one node. Each said node receives an AC waveform at an AC power terminal from an AC power line.
Each node includes a power supply for providing DC power at first and second DC power terminals for operating the node and for communicating through the data line with the other nodes. The second DC power terminal voltage level corresponds to the dominant signal level. Each node has an interface circuit comprising i) a pull-up impedance connected between the first DC power terminal and the node""s output data terminal, and ii) a variable impedance connected between the node""s output data terminal and the second DC power terminal. Each interface circuit has a control terminal. The variable impedance in each interface circuit provides a first impedance value substantially smaller than the pull-up impedance value responsive to an output data signal at the control terminal having a first level, and an impedance substantially larger than the pull-up impedance value responsive to a second level of the output data signal at the control terminal. The variable impedance""s first impedance value holds the data line voltage level substantially at the dominant signal level irrespective of the impedance of the variable impedances in other nodes.
Each node has a phase detector receiving the AC power terminal waveform and providing a synchronizing signal having level changes in predetermined time relationship to predetermined points in the AC power terminal waveform. A signal generator in each node receives the synchronizing signal and provides the output data signal to the control terminal. Typically, the signal generator will be a microprocessor. The generator changes the output data signal level in predetermined time relationship to the level transitions in the synchronizing signal. With all the nodes using the same AC waveform to synchronize data transmission, it is easier to resolve message collisions.
Another advantage of this feature is that three wires are sufficient to carry both data and power to each of the nodes. By adding a rectifying power supply to each node, the AC lines can provide DC power for operating the node and for transmitting data on the data path.
These synchronized nodes can include in each of them, inexpensive features that are very helpful in diagnosing a number of different system problems arising from either miswiring or from node or connection failures, and in monitoring and analyzing operation of the node. By proper powering of an indicator element such as an LED, it is possible to signal so a human can infer operating status and modes for each of the nodes. One aspect of our invention provides analytical tools that automatically perform fault diagnosis and operating analysis for the installer or service person.
Even though the nodes are connected by only three lines, it is still possible to miswire a node to the system. We have devised fault diagnosis software and hardware that operate cooperatively to detect such miswires and provide an indication of them to humans.
Two types of miswires can occur. In the first, the data path is connected to the AC power terminal from which the synchronizing signal is taken. Software uses the internal microprocessor clock to measure the times between the level changes in the synchronizing signal. When these are outside an expected range, this first type of miswire may exist. The reason is that a data signal""s level changes will not mirror that of the AC waveform. We use a different testing procedure to detect when the data line is connected to the other AC power terminal. In this case, an AC line is connected to provide the AC waveform at the data terminal. The AC waveform appears to be a uniform train of high and low voltage levels, which is different from a normal data signal. This situation can also be detected with software by using the internal microprocessor clock.
A first concern in detecting miswires is that the miswired node receives AC power. In our system, the rectifying power supply in each node comprises first through fourth diodes forming a bridge circuit. To provide operating power for the node, the node has fifth and sixth diodes connecting the data terminal in bridge configuration to the first and second DC power terminals. By bridge configuration, we mean that the fifth and sixth diodes are connected between the data terminal and the DC lines so that DC power is still supplied to the DC power terminals even if one of the AC power terminals is connected to the data path rather than to AC power.
A first error indicator provides a humanly discernable error indication responsive to a first error signal. Typically, this indicator will comprise an LED controlled by a microprocessor to flash in a certain pattern. A synchronizing signal tester receives the synchronizing signal and measures interval lengths between successive synchronizing signal level changes. The signal tester compares these measured interval lengths with a predetermined range of interval lengths, and provides the first error signal to the first error indicator responsive to a measured interval length falling outside of the predetermined range of interval lengths.
A second error indicator provides a humanly discernable error indication responsive to a second error signal. The second error signal in dictates the miswire of the data line to the AC power terminal not furnishing the synchronizing waveform. A data value tester receives the data signal and if the sequence of level changes in the data signal suggests that the data signal is in fact the AC waveform, supplies the second error signal to the second error indicator. As mentioned, an AC waveform applied to the data terminal of the node has a detectable pattern.
One version of this data value tester tests for a long train of alternating high and low logic levels at the data terminal, each of these alternating levels persisting for a single bit interval. The data value tester includes a memory element recording data signal levels responsive to a bit value signal. A counter element in each data value tester records a count value and providing a count signal encoding the count value. The count value is altered by a predetermined delta value responsive to an alter count signal, and sets to a predetermined cleared value responsive to a clear count signal.
An analyzer element receives the data signal and the synchronizing signal, and responsive to level changes in the synchronizing signal providing an alter count signal to the counter element. The analyzer element compares the most recent level of the data signal to the data signal level recorded in the memory element, and if logically identical, providing a clear count signal to the counter element. Then the analyzer element provides a bit value signal to the memory element encoding the most recent level of the data signal.
A comparison element receives the count signal and provides a second error signal to the second error indicator responsive to the count value encoded in the count signal reaching a predetermined fault value different from the cleared value.
Another diagnostic or analytical feature is an indicator element that provides a human perceptible indication whenever and only when the node in which the element is present is actively transmitting on the data line. This feature is not limited to systems receiving AC waveforms for either synchronization or power, but is intended for systems connected by a power line, a data line, and a common line. Each node has an interface circuit for connecting to the data and common lines. The system includes at least one pull-up resistor connected between the power and the data lines.
The nodes each have an interface circuit having an isolation element having a first terminal connected to the data terminal and a second terminal. Each module also has a switch for connecting the isolation element""s second terminal to the common conductor responsive to a first level of a local data signal and for disconnecting the isolation element""s second terminal responsive to a second level of the local data signal. An indicator element in each module is connected between the power conductor and the isolation element""s second terminal. The indicator element includes a preselected impedance. When the switch is conducting and there is power applied to the indicator element, the indicator element provides a human perceptible indication while the switch is closed. If the element is a light-emitting diode, the indication is the light emitted. If the element is a sound generator, then the module will generate a characteristic sound when the switch is closed.